The present invention relates generally to the selective voltage binning, and more particularly to adjusting voltage based upon electronic chip identification and location versus across chip value.
As computing systems become smaller and faster, power lost due to current leakage and overall power use increases. Integrated circuit designers are increasingly attempting to raise chip performance but are limited by maximum power limits imposed at the system level. In general, the fastest components of an integrated circuit chip are forced to run faster and at higher voltages in order to achieve enhanced chip performance. Such increased voltages lead to greater current leakage, and therefore, to greater power consumption and overall greater power loss.
On-chip variation (OCV) is a recognition of the intrinsic variability of semiconductor processes and their impact on factors such as logic timing. Historically, as well as operating temperature, timing variation was primarily a consequence of subtle shifts in manufacturing conditions that would lead to integrated circuit chips from one batch of wafers being ‘slow’ or ‘fast’ relative to nominal estimates. To account for this, design would run two sets of timing analyses: one for the slow corner and one for the fast corner. If the design passed these two tests, the chip could be considered to have met its timing constraints.